1 files changed, 60 insertions, 0 deletions
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h
new file mode 100644
index 0000000..59b473c
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h
@@ -0,0 +1,60 @@
+// Address Space Parameters
+
+`define ROWSTART        8          
+`define ROWSIZE         12
+`define COLSTART        0
+`define COLSIZE         8
+`define BANKSTART       20
+`define BANKSIZE        2
+
+// Address and Data Bus Sizes
+
+`define  ASIZE           23      // total address width of the SDRAM
+`define  DSIZE           16      // Width of data bus to SDRAMS
+
+//parameter	INIT_PER	=	100;		//	For Simulation
+
+//	Controller Parameter
+////////////	133 MHz	///////////////
+/*
+parameter	INIT_PER	=	32000;
+parameter	REF_PER		=	1536;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+////////////	100 MHz	///////////////
+parameter	INIT_PER	=	24000;
+parameter	REF_PER		=	1024;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+///////////////////////////////////////
+////////////	50 MHz	///////////////
+/*
+parameter	INIT_PER	=	12000;
+parameter	REF_PER		=	512;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+
+//	SDRAM Parameter
+parameter	SDR_BL		=	(SC_PM == 1)?	3'b111	:
+							(SC_BL == 1)?	3'b000	:
+							(SC_BL == 2)?	3'b001	:
+							(SC_BL == 4)?	3'b010	:
+											3'b011	;
+parameter	SDR_BT		=	1'b0;	//	Sequential
+							//	1'b1:	//	Interteave
+parameter	SDR_CL		=	(SC_CL == 2)?	3'b10:
+											3'b11;
+